Field of the Invention
Embodiments of the present invention relate to a semiconductor device such as a power semiconductor module.
Discussion of the Background
FIG. 11 is a cross-sectional diagram showing the principal parts of a conventional semiconductor device having a structure similar to the one described in Japanese Patent Application Laid-open No. 2009-64852 (“Patent Document 1”). A power semiconductor module as the conventional semiconductor device has a DCB (Direct Copper Bonding) substrate 104, a conductive-patterned insulating substrate, which is configured by an insulating substrate 101 and copper circuit patterns 102a, 102b formed on the front and back of the insulating substrate 101. This power semiconductor module also has a copper block 103a fixed to the copper circuit pattern 102a of the DCB substrate 104 by means of diffusion bonding or the like, and a copper block 103b fixed to the copper circuit pattern 102b of the DCB substrate 104 by means of diffusion bonding or the like. This power semiconductor module has a semiconductor chip 106 having the rear surface thereof soldered or the like onto the copper block 103a by a bonding material 105, a conductive post 108 soldered or the like to an upper electrode of the semiconductor chip 106 by a bonding material 107, and a printed circuit board 109 with the conductive post 108. The power semiconductor module further has a sealing resin 111 for sealing the semiconductor chip 106, the DCB substrate 104, and the printed circuit board 109. Reference numeral 110 represents an external lead terminal.
Japanese Patent Application Laid-open No. 2009-94135 (“Patent Document 2”), on the other hand, describes that, when soldering a power semiconductor chip to a DCB substrate, a plurality of stress relaxation dimples are provided to the rim of a conductive pattern along the border between the ceramic substrate and the conductive pattern.
Japanese Patent Application Laid-open No. 2009-88176 (“Patent Document 3”) describes that an outer circumferential rim of a metal layer bonding a circuit member and a support base together has irregularities, as viewed planarly, in order to reduce a thermal stress applied repeatedly to a heat dissipation base.
Moreover, Japanese Patent Application Laid-open No. H8-274423 (“Patent Document 4”) discloses a ceramic circuit board configured by bonding a metal plate, such as a copper plate, to a ceramic substrate by means of a direct bonding method or active metal soldering method, wherein intermittent grooves are formed on the inside of an outer circumferential rim portion in a linear manner along, for example, the outer circumferential rim portion at predetermined intervals, the outer circumferential rim portion being located on the side opposite to the bonded surface of the copper plate. Patent Document 4 describes that such configuration can effectively prevent the ceramic substrate from cracking or a decrease in the intensity thereof even when a cooling/heating cycle is employed.
In a resin-sealed type semiconductor, the adhesion of the resin to the embedded members has a significant impact on the reliability of this semiconductor. In the structure shown in FIG. 11, a stress occurs between the sealing resin 111 and the copper circuit patterns 102a, 102b made of copper in the vicinity of the insulating substrate 101, due to the difference in linear expansion coefficient between the insulating substrate 101 made of ceramic and the copper circuit patterns 102a, 102b, which configure the DCB substrate 104. This leads to a problem in which the DCB substrate 104 and the sealing resin 111 peel off of each other.
When the DCB substrate 104 equipped with the semiconductor chip 106 and the sealing resin 111 continue to peel off of each other, a stress concentrates on the bonded section between the semiconductor chip 106 and the copper block 103a as well, deteriorating the bonded section, which becomes a cause of failure of the semiconductor module.
In particular, insulation failure occurs when the peeling between the copper circuit pattern 102a and the sealing resin 111 develops to affect the insulating substrate 101. Even if the sealing resin 111 is adhered only to the insulating substrate 101 and peels off of the copper circuit pattern 102a, stress concentrates on a part of the insulating substrate 101 near the copper circuit pattern 102a, generating cracks in the insulating substrate 101 and consequently resulting in, again, insulation failure.
A power semiconductor module equipped with a WBG (Wide Band Gap) element such as a SiC (silicon carbide) device, which has recently been employed, has a wider operating temperature range than a conventional power semiconductor module equipped with a Si (silicon) device and is therefore driven at temperature equal to or higher than the temperature for driving the power semiconductor module equipped with a Si device (Tjmax≧175 C.°). This further increases the level of thermal stress and is assumed to cause the peeling of the sealing resin 111 described above, deteriorating the reliability of the power semiconductor module.